Renesas is seeking a Sr. Staff Test Engineer to support new product test development for our Performance Computing Power (PCP) business unit located in Catania, Italy .
This position will work on leading edge power management products that have significant business impact. You will be required to apply conceptual thinking to understand advanced issues and their implications. It will be necessary to exercise independent judgement in methods, techniques and evaluation criteria.
Key Responsibilities
* Test development for power management and mixed signal products, including: ATE platform selection, design for test (DFT) implementation, test plan development, ATE hardware design, and delivering robust & cost-effective test solutions
* Collaborating with other local and worldwide functional teams to align test strategies with overall business and quality objectives
* Ensuring test solutions meet coverage requirements and are robust in production
* Analyzing ATE test results using statistical analysis applications to help improve repeatability and stability
* Providing overall planning support for test development projects, including setting development timelines, budgets, expected test times and keeping projects on schedule
Qualifications
* Bachelor’s degree or greater in Electrical/Computer engineering or Computer science.
* 8+ years of experience working with Automated Test Systems (ATE); Microflex & Advantest 93K preferred. ETS364/800 a plus.
* 8+ years of experience in ATE test development for analog, digital and mixed signal.
* Experience in programming such as C++, basic, Perl, python, etc.
* Experience in testing and collecting data on IC chips or circuits using standard tools such as oscilloscopes, multimeters, spectrum analyzers, etc.
* Experience with data analysis and GR&R methodology. JMP application knowledge is a plus.
* Proficient with ATE analog/digital instruments, PCB layout parasitic reduction, and strong debug/troubleshooting experience
* Hands-on experience in debugging analog products with serial bus interfaces
* Travel 0-10%